0.2 Hz DSP filter

Yes -- you're designing a FIR filter when you want an IIR filter. Expect to use 2x taps as the filter order for an IIR, but you need a much lower order filter.

Search for "IIR Filter" on the net. Be way careful about the degree of precision -- if you use the typical bilinear filter forms you're going to need (100Hz/0.2Hz)^2 more precision than your input data, or 18 bits. This can be a bummer when you have 16-bit data. You can use a state-space filter that trades off more computation for lower precision (i.e. you'll get it down to 9 bits instead of 18, but you'll need six multiplies for a 2nd-order filter instead of 4).

For an FIR filter with 16-bit taps and 16-bit data you can expect some setup (10 to 50 clocks) then one clock per tap. IIR filters tend to be more difficult to code effectively. You could probably do this with an

8051 and some clever coding tricks, so unless you're really running that 2181 slowly you just don't have to worry.

You're welcome. You may want to ask the question again on comp.dsp if you're not happy with what you've heard here.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm trying to replace a 0.2Hz 2nd order LP active filter with a similar DSP filter. It doesn't need to have a very sharp cutoff but the .6 Hz information needs to be down by ~30dB. It should continued down to -50 to

60 db from there.

My question is how do I determine the number of taps required? if taps are roughly equivalent to the order then 2 or three should get me. However. with a 100Hz sample rate from the A2D my ScopeFIR says I need ~700 taps. Am I doing something wrong?

What is the design algorithm for a analog guy that wants to replace analog filters with a digital one?

Also, I'm using a ADSP2181 processor. How do I calculate how many clock cycles it takes to execute a single tap on the filter?

Thanks

Look on the microchip site, there are several application notes on implementing digital filters.

IMO the same sampling theorem holds as for doing FFTs. The sampling memory has to be about as long as a period of the lowest frequency you wish to process. So these

100Hz divided by 700 go down to 0.15Hz. This doesn't mean that you need all 700 taps unequal zero. There are decimatiuon algorithms that allow you to process only every N-th sample, IIRC.

I'd recommend digging up some theory.

Rene

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Ing.Buero R.Tschaggelar - http://www.ibrtses.com
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If you search with google you should find a few DSP design programs. At least one of these has a demo version available, limited to 7 sections IIRC, but it should help you get started. Your filter spec seems to indicate

60db/decade - that's pretty sharp, BTW.

-- Nicholas O. Lindan, Cleveland, Ohio Consulting Engineer: Electronics; Informatics; Photonics. To reply, remove spaces: n o lindan at ix . netcom . com psst.. want to buy an f-stop timer? nolindan.com/da/fstop/

It depends of your perspective - 3 pole filters aren't usually regarded as bleeding edge stuff. But at such low frequencies, one would hope for a correspondingly low sampling rate, or else a double-precision implementation.

Tony (remove the "_" to reply by email)