Logic Question

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

View in fixed-pitch:

__ A ---o-------------| \ | | )o-. | .--|__/ | | | | | __ | | __ '--| \ | '--| \ | )o--o | )o---A xor B .--|__/ | .--|__/ | | | | | __ | | '--| \ | | | )o-' B ---o-------------|__/

I didn't explain well enough...

When B is low, A propagates to the output non-inverted... 2 stage delay

When B is high A propagates to the output inverted... 3 stage delay

I'm looking for some scheme where both paths are equal delay.

I can see how to do it in PECL (which is really analog :-), but not in CMOS :-( ...Jim Thompson

I vaguely remember seeing a picture of this done at the transistor level, in CMOS, with a structure reminiscent of a trimmed-down Gilbert cell mixer.

But I'm not sure if I could give the actual circuit if my life depended on it.

At least in the 1970's ECL 10000 gate the basic logical element was the OR/NOR gate consisting of an differential amplifier followed by emitter followers.

The ECL 10K Excusive-OR gate was implemented by a cascaded Gilbert differential stage followed by level shifters,

Yes, but it wasn't called a Gilbert cell yet ;-)

(In the very early '60's, I was at Motorola, where ECL was first developed... Jan Narud was my first non-academic boss.) ...Jim Thompson

A small look-up table?

An XOR is a convenient structure to allow a control signal to invert or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

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I am not sure where you get the uneven propagation delays. Perhaps you are considering both logic levels switching at one time? I would assume the logic inversion control input would already be quiescent.

(thinking out loud here) Exclusive OR gates are quite simple complex gates (confusion intended)

Simply English text stated A or B but not both.

This equates to three simple gates

an OR gate = A+B 'this is the OR part, obviously an NAND gate = NOT(A*B) 'this is the not both part and one to combine the logic on the output 'this is what combines the two conditions AND = (A+B) * (NOT(A*B)

Now when A input is true (overall inversion) the A+B gate becomes blocked at the output AND gate when B goes true. Yup, the active NAND input gate NOT(A*B) has an extra inversion stage to control the O/P AND gate.

When A input is false (no overall inversion) the A+B gate predominates at the output of the AND gate when B goes true. The inactive NAND input gate NOT(A*B) is not functioning in the output signal through the O/P AND gate.

The same number of simple gates are used each logic but the transistor stages are the same.

Perhaps slip a simple buffer into the output of the input OR gate to increase it's propagation. Now you would have to find one with the same number of stages as the NAND has for inversion hmmmm... not likely.

What type of logic family are you attempting to do this with? Logic insides need to be known for this one.

Spec sheets are needed to spec propagation delay.

mike

An XOR is a convenient structure to allow a control signal to invert or non-invert another signal.

Trouble is (as classically done) inverting has 3 stage delays, while non-inverting has only 2.

Anyone know of a configuration that has symmetric delays?

Thanks!

(I'm rolling my own at the device level so anything goes :-)

...Jim Thompson

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One other comment here.

This whole thing may be BS as NAND gates were a more natural logic using transistors as they took less transistors to create. NAND and NOR gates can be accomplished with one stage or transistors.

AND and simple OR gates had an extra inversion stage to make them operate with their logic and thus had more propagation delay.

Been a long time since I studied the inside circuitry of logic gate families. My boss insisted we knew everything about an IC before tackling any repairs. Of course we usually fixed the problem when he went to answer the phone. Got years of chasing electrons experience, though.

mike

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Hello:

Have you tried transmission gates? See:

Best Regards

Steve Sousa

Never rolled my own at the device level but can you drive A through a tristate inverter and a tristate buffer and then use B to select the output?

I trying to simultaneously get Q and Qbar with equal delay.

I'm concluding the best I can do is fudge some sizing to somewhat equalize delay paths. ...Jim Thompson

Do the delays have to be symmetrical? In other words, if we give you an A XOR B where A is the signal and has 3 stage delays regardless of B state, will B ever be used as the signal (requiring 3 stage delays for either A state?

I do remember it. I saw it inside a TTL EXOR circuit, maybe the 7486. Two NPN's, E and B cross connected to open collector drivers (A and B), output taken from connected collectors, with a pull-up. At least it is symmetrical, but maybe not too fast.

A ---- E1 -- B2 pull-up | C1 -- C2 --+--- OUT

B ---- B1 -- E2

Regards, Arie de Muynck

Since you are rolling your own start with a 7474 D flop with /pre and /clr. That would give you your Q and /Q. Strip out the clk gates and just drive the /pre and /clr. The old data sheet for the SN7474 is still on the TI web site with the TTL schematic. The newer parts like the 74ahc74 have logic diagrams. What is your A->out timing budget?

And of course it needed some pull-ups on the O.C. drivers as well...

pull-up | A --+-- E1 -- B2 pull-up | pull-up C1 -- C2 --+--- OUT | B --+-- B1 -- E2

Arie

Oh, much better would be to make a differential driver circuit. I'd suggest some relevant chips, but I think you said you were building it from primitives.

Jon

I'm doing a high-speed 3.3V to 5V translator, where "5V" may be just about anywhere 3V to 5.5V ;-)

But I think I've figured out a way to avoid the funny "lumpy" risetime I'm seeing. Looks like, rather than perfect delay match, sequencing delay mismatch depending on transition direction may smooth it out. ...Jim Thompson

How about something like this:

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant