FET models

theres been an improvement discused in sci.electronics.design for sub threshold operation of FET models.

Colin =^.^=

I remember Winfield Hill's note of 6/24 concerning altering the model for the Fairchild FQD2N100 1KV FET. BUT the original model does not work properly, and i am a bit unfamiliar with SPICE and the mod that was made - so it is not possible to evaluate the result (there was no observable difference). Do you have a decently working model set (original & modified)?

[snip]

Do you have any accurate data for this region?

I'd like to try modeling it with a higher level model, rather than patching onto a Level=1 or 3 model.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
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|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

yes thats the one i was thinking of, there were several threads, one gave modified/unmodified models although i cldnt put my finger on it straight away, one also mentioned a method of combining the log characteristic of a diode with the input. Im afraid i didnt have any more to offer than pointing you there. good luck.

Colin =^.^=

Most non-logic power FETs seem to follow (Vgs1-Vgs2) =

0.25*log10(Id1/Id2); logic FETs have a different slope. What really bugs me, is if i "slide" the straight line (to the right) along a log (vert) / linear (H) scale to cover 6-7 decades instead of the original 2 decades, the calculated factor changes from about 0.25 to about 0.17 and i cannot figure out what is wrong.

[snip]

See attachment at...

Newsgroups: alt.binaries.schematics.electronic Subject: Power MOS, Log(ID) versus Gate-Source Voltage - LogIDvsVGS.pdf Message-ID:

All the discussions here, S.E.D and in A.B.S.E about cobbling up a "patched" power MOS Spice model to cover low-voltage-low-current characteristics have always struck me as dangerous, fraught with possibility for error in other parameters.

The attachment shows how Level=7 seems to naturally cover the region.

So I think two things are in order...

(1) Harass Power MOS manufacturers to provide a correct Spice model

or

(2) Roll you own, but use Level=7 parameters rather than patching a lower level model.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Just amusing myself, reading up on the subject, the EKV model may be best.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Mike, Is that an LTspice-specific model or is it a subcircuit?

Does it solve Win's low-current fretting issues?

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Jim,

Level=7 will handle sub-threshold, but for many applications there's an even greater discrepancy between the model and the part -- that being the way it stores charge, particularly the Miller capacitance. The only way I've seen that handled properly in a native SPICE device is in LTspice's VDMOS device, though the DC curves of that is just a Level 1 MOS with no sub-threshold modeled.

The deal with the charge is that the vertical double-diffused MOSFET qualitatively behavior entirely differently than a monolithic device, particularly w.r.t. the Gate-Drain capacitance.

--Mike

Jim,

EKV's forte is really about D.C.(and some think that it a break- through for a compact description of the monolithic FET). But I haven't seen the EKV charge model solve the Gate-Drain capacitance modeling problem of a VDMOS power transistor. The VDMOS transistor typically used as descrete power transistors just fundamentally stores charge differently than the monolithic MOSFET.

--Mike

Jim,

It's a LTspice specific device. An intrinsic new SPICE device, not a subcircuit and without internal nodes. It's documented toward the end of the section of the help LTspice=>Circuit Elements=>M. MOSFET

No, not at all. It has no sub-threshold. It just gets the charge storage right. It's forte is that it switches correctly because it has the Miller capacitance correct. It does not handle the Win's problem with sub-threshold. That's a real problem, too. If you wanted to fix both, an approach would be to use a subcircuit with a Level 7 for DC(with no charge storage) in parallel with an LTspice VDMOS with no conduction, but supplying the charge storage. I haven't added the power MOSFET's sub-threshold to LTspice's VDMOS device because it only comes up, well, in sub-threshold, not when you're actually turning the thing on and off or even in proper linear range. Besides, people can cobble some sub-threshold behavior in when they need it.

--Mike

Oh...you mean it uses an inductor?

Kevin Aylward snipped-for-privacy@anasoft.co.uk

SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

Kevin,

Inductors don't store charge, they store flux. The VDMOS Miller capacitance behaves fundamentally differently than that of a monolithic device. See LTspice help documentation for the VDMOS charge model.

--Mike

Ahmmm...indeed they do. According to relativistic electromagnetics, all magnetic and electric phenomena are one and the same, but observed from different reference frames.

What we identify as magnetic or electric is simply one of convieniance, not physical reality.

Hint: why should a magnetic field suddenly appear just because an

*observer* moves past a charge?

Hint: just what do you propose "magnetic flux" *actually* is? Hint: just what do you propose "electric flux" *actually* is? Hint: photon exchange.

Kevin Aylward snipped-for-privacy@anasoft.co.uk

SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

Sno-o-o-o-ort ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Kevin,

Completely irrelevant for lumped-constant reactances and doesn't change the fact that a power MOSFET's Gate-Drain capacitance is fundamentally different then that of a monolithic MOSFET, no matter what reference frame is used.

Your penance shall be to hand write "Inductors don't store charge, they store flux." 100 times and tape it to your monitor for 2 days.

--Mike

ROTHFLMAO.

You certainly walked right into that one with your eyes closed Micky laddie.

So, fundamentally different, so, you cliam that gate capacitance is due to moon cheese then?

As Inspector Clouseau would say, "you fooool"

First, it was obvious to any with any sense that I was trolling.

Second, regarding your last comment, as a point of fact, you should indeed stick to what you know, like spice matrices.

I will tell you once more. *All* electromagnetic phenomena is due to charge. Period. End of story. All electromagnetic energy storage is by way of the effective charge position and charge motion. Charge is a number that identifies aspects of the momentum flux of photons. "Magnetic stuff" does not exist. Its all photons mate. Flux is no more than a distribution of photons... oh dear...never mind...stick to software...

Kevin Aylward snipped-for-privacy@anasoft.co.uk

SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

Kevin,

See the reference(LTspice help pages). It's because of the drain being on the back of the die. The functional dependence of the gate-drain charge on the terminal voltages is fundamentally different then that of monolithic devices. As this is the Miller capacitance, it fundamentally changes the the switching behavior of the grounding source device. Fundamental in that the behavior is qualitatively distinct. It's why MOSFET vendors usually have to use a subcircuit to model their MOSFET's, but LTspice has an intrinsic device with an appropriate charge model.

I didn't said it was or wasn't. But you're wrong, you need space and time too, though. Charge by itself won't cut it. And moving charge has behavior to be reckoned with. And the laws of physics aren't invariant in non-inertial frames. There's no inertial frame which converts all of the general inductor's B-field to an E-field. The formulation of lumped constant reactances has no concept of space, you just have to trade things like E-field times distance with electromotive force. Inductance and flux are as real as they are useful, no matter how much you would like to dismiss it. Of course the joke is that I'm the one here that's the physicist in real life and you're not.

You were supposed to put your penance work on the FRONT of your monitor for two days!

--Mike

"Capacitance stores charge, inductance stores flux." Mike Engelhardt 2005

Hello,

I have a small comment to the discussion. It is not too helpful at the moment, but it shows some perspective that may become real in the future.

The problem to make a compact transistor model happens to be close to the goal of Model Order Reduction. We have contrasted compact modeling with model order reduction in

MST MEMS model order reduction: Requirements and Benchmarks

preprint is at

Well, at present model reduction cannot be used in the case of transistor, yet it is already working extremely well for linear systems. You can try it for ANSYS models with our free software

I hope that one day mathematicians will extend it to nonlinear problems as well.

Best wishes,

Evgenii Rudnyi

--
http://Evgenii.Rudnyi.Ru/