As promised, an exposé of an issue with the Rigol DS1052E oscilloscope in my latest video blog:
Dave.
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You corrected the number of PLLs in the FPGA, how do they get the clocks' phases aligned? I'm no expert on digital scopes, but I suppose the clock frequency changes depending on the time base? Do they just drop some ADCs and keep the frequency, thereby permitting the use of trace delays to get the 100ps delays or what? Are the GS/s figures real time or equivalent time? I think it is possible Rigol tests the ADCs and bins them in-house. Do you think they might run the power supply a bit "hotter" to get the parts to work at higher clocks?
Does this Rigol claim to do 1Gsps on non periodic signals? If not (like other sampling scopes), perhaps they're just sliding the phase of the A-D's while still clocking them within their rated specs.
Did you ever measure the clocks to the A-D chips?
Bob
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Obviously their engineers grew up over-clocking AMD/Intel motherboards then :)
I was initially concerned about the temperature the ad9288-40 is running at when it's over clocked from 40 to 100Mhz, which won't be an issue since they have a version that runs at 100Mhz, probably using the same die.
I'd also be concerned about whether the 40Mhz part can convert at
100Mhz, but looking at the data sheet, there doesn't seem to be any perceivable difference in the switching/dynamic characteristics, apart from one each having a specified maximum conversion rate.As long as the scope perfoms to spec, I don't see anything wrong otherwise
Do the scopes work?
John
Beats me. Could be as simple as fixed tuned gate delay inside the FPGA, or could be some more complex system that auto-calibrates perhaps.
Only when required when the memory is full. On short memory mode (1GS/s, 16KB) a relay clicks in at 100ns/div and it tells you it's doing 1GS/s on 50ns/div to 5ns/div. No such click occurs when in long memory mode (500MS/s 1Mpoints), and it stays on 500MS/s up to 100ns/div. The relay is thus most likley switching the input signal between either 5 or
10 ADC's depending upon the requirement. 1GS/s real time of course, that's been the selling point of these Rigol scopes for the last 5 years or so.I don't think so, likely they have just done exhaustive testing of these parts to ensure the work. Binning each one in house would be possible, but messy. Perhaps AD are the ones pulling the swifty and charging a huge premium (almost 3 times) for the exact same part?
Dave.
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Yes, that's always been its big selling point. 1GS/s real-time.
It also has a selectable equivalent time sampling mode (up to 10GS/s), but you have to specifically select this through a menu. In this mode the 1Mpoint memory comes in at 100ns/div.
No, I haven't open my unit. But bet your bottom dollar they are 100MHz, simply no other way to do it.
Dave.
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Yep, they work. So Rigol are obviously getting away with it by hook or by crook. If AD are deliberately under-speccing their normal chips, then it's a clever ploy by Rigol to exploit it.
Dave.
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It could have been a purchasing error, that actually works. Or, the parts marked as 40 don?t meet the specs over temperature for a
100/80 mhz clock. Perhaps NL specs are not met but Rigol can compensate for the error. I've seen -40c to 85c parts work beyond the rated specs, with some additional error.Cheers
PS: Another piece of consumer electronics that was on the shelves for
10 years was the Commodore 64. I'm sure it underwent internal changes but it was the same machine for years.
Tuning gate delays in an FPGA doesn't work. Routing is over half the delay and there is no way to fix that part. Every time you "wire" the part it'll have a different routing and your delays will be off. Indeed, the idea is to make sure you don't rely on placement or routing.
ver
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So give it a 1 Ghz signal and see if it it looks right then.
Why not? I'm pretty sure a 50MHz and 100MHz are exactly the same too.... :)
I meant a 50MHz and 100MHz scope up there.
Maybe, and I've mentioned this in a previous blog comment. There is a chance the 50MHz and 100MHz model front ends are identical except for maybe some different value parts on the 50MHz model to limit the bandwidth. Would be interesting to see both circuits side-by-side. Given that both sample at 1GS/s and everything else is indentical too, modding the 50MHz unit might just be possible.
Dave.
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blackhead wrote in news: snipped-for-privacy@s31g2000yqs.googlegroups.com:
Umm, no. Ever heard of Nyquist?
Plus to see anything like a signal for your eye's benefit, you're better off with x10 sampling.
So 100MHz is more on the mark. Does it allow you to simply plot the points without the "join the dots"?
BTW if you had exactly 1GHz going in, and it manged to sneak pass the front end, you'd end up with a straight line at some DC level.
Ray
Yep. You can choose between dots, linear ("join the dots") vector intepolation, or sinX/x interpolation.
That would be a neat trick!
Dave.
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innews: snipped-for-privacy@s31g2000yqs.googlegroups.com:
I have heard of Nyquist, just forgot to apply him in this case :) There will be an anti aliasing filter in the front end so you wont see much if you put in anything close to half the sampling rate = 500Mhz. Or maybe Rigol has decided to cut corners and got rid of it completely ;)
and you forgot about the analog bandwidth too, that's kinda important!
Err, the front end bandwidth is only 50MHz! Kinda hard for any signals higher than that to sneak past, as Ray said.
Dave.
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We overclock/overstress parts when there's a substantial payoff. One Freescale uP is rated for 16 MHz clock, actually gets wonky at 44, so we run it at 20. One microwave schottky diode is rated for 2 volts reverse, leaks a bit at 7, so we use it at 4. Adding a heatsink to an FPGA can buy some timing margin. Some diodes and cmos parts leak four or five orders of magnitide less than the datasheet guarantees. An
0603 resistor can dissipate a quarter of a watt safely. The trick is to take calibrated risks where there's demonstrated margin and big paybacks, and take zero risk everywhere else.John
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