Grundig Satellit 300 whinge

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The Satellit 300 was a digital PLL synthesis radio receiver from the
80s, and I bought it new, so I must have had it for getting on for
thirty years.

http://www.radiomuseum.org/r/grundig_satellit_300.html

I suppose I can't complain that much given that it still worked until I
dropped a wooden curtain rail onto it. The outside was unmarked, but it
would no longer pick up MW (though VHF was OK, don't know about the
other bands), the tuning wheel didn't work, and the illumination for the
LCD panel was absent.

The first problem suggested an issue with the ferrite rod antenna (not
used for VHF of course), and a minute or so after I'd opened the thing
up I spotted a broken connection. The second problem was also a wire
that had broken off the tuning wheel mechanism. The third was a broken
filament bulb.

The first two faults would probably not have occurred if the wiring had
any slack in it at all.

Also, this was an expensive radio - hadn't they heard of headers?

http://members.optusnet.com.au/sylviae/satellit3.jpg
http://members.optusnet.com.au/sylviae/satellit4.jpg

Several more things broke while I was trying to put it back together,
though it's all working now - I think.

Sylvia.


Re: Grundig Satellit 300 whinge
On Mon, 05 Dec 2011 20:12:05 +1100, Sylvia Else

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Gosh, what a hairball. Hadn't these people heard of ribbon cables?
Hadn't they heard of electronic packaging in general?

Packaging is half the job in this business. As my old mentor Melvin
Goldstein used to say, when you've got the schematic, you're 10% done.

John



Re: Grundig Satellit 300 whinge
On Dec 5, 4:24A0%pm, John Larkin
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Half the job? I seemed to spend more time sorting out connectors than
I ever did on picking the right active components, and I used a great
many different active components

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If the schematic was drawn with a clear idea of how the active devices
were going to be laid out and connected to the outside world, this
might be right. In real life the packaging has a way of getting parts
of the schematic redrawn.

When you start shipping your timing signal between boards on coax
cable, routed through mixed signal DIN-41312 connecters, and find
youself stuck with using triple-extended Eurocards to make room for
enough connectors, the schematic gets to be a finally minor part of
the documentation.

--
Bill Sloman, Nijmegen

Re: Grundig Satellit 300 whinge
On Mon, 5 Dec 2011 10:45:28 -0800 (PST), Bill Sloman

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A schematic should certainly include all the connectors, and their
part numbers and pin numbers, and all the mounting holes' LEDs, and
test points. How else could you lay out the PC board?

In real life the packaging has a way of getting parts
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Not in my world.

John


Re: Grundig Satellit 300 whinge
On Dec 5, 8:11A0%pm, John Larkin
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How indeed? But the realities of printed circuit layout - like things
sticking out of other boards - have a way of adjusting the original
magnificent simplicities.

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We already knew that you didn't live in the real world. Presumably
these things happen behind your back - what the boss doesn't know
doesn't upset him ...

--
Bill Sloman,


Re: Grundig Satellit 300 whinge
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[...]

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My world is the same as John's is. Maybe you live in a different one?


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Da boss usually sits in design reviews so da boss gets to know if this
should happen :-)

--
Regards, Joerg

http://www.analogconsultants.com /

Re: Grundig Satellit 300 whinge

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Joerg, Joerg, Joerg!  All you contribute here is feeding trolls.
Bye... again.
        
                                        ...Jim Thompson
--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Re: Grundig Satellit 300 whinge
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Jim, Jim, Jim! When do you learn about modern newsreaders that allow to
selectively pick what one wants to have displayed ...

Tsk .. tsk .. tsk :-)

--
Regards, Joerg

http://www.analogconsultants.com /

Re: Grundig Satellit 300 whinge
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Please, Joerg, don't bait the old prejudicial fart.

Re: Grundig Satellit 300 whinge
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The worlds we perceive are clearly different - I suspect that
imperfections in perception have more to do with the differences we
report than any difference in objective reality (whatever that may
be).

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 A0% A0% A0% A0% A0% A0% ... Presumably
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Design reviews don't go on for ever - though sometimes it feels that
way - and some details are inevitably glossed over, particularly the
ones that might upset the boss. And John seems to be easily upset - he
certainly complains about being insulted surprisingly often.

--
Bill Sloman, Nijmegen

Re: Grundig Satellit 300 whinge
On Mon, 5 Dec 2011 19:28:46 -0800 (PST), Bill Sloman

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I draw schematics, fill out the form to create new library parts,
define the outline/mounting/connectors/heatsinks/LEDs, do the stackups
and trace impedance rules, plan and often do the parts placement,
oversee layout, and check/tweak the PCB before it's Gerbered. I often
lay out critical high-speed or low-level sections myself. Once in a
while I do an entire board, just to keep in practice.

We Gerbered this today:

ftp://jjlarkin.lmi.net/ESM_pcb.gif

The thing in the middle is an LTC2242 250 MHz, 12-bit ADC.

The only new thing, of late, is that I don't assign FPGA or uP BGA
pins on the initial schematic. That would almost always make routing
impossible. We have a net name convention like

NAME_F     FPGA i/o

NAME_P_FL  lvds pair +
NAME_N_FL  lvds pair -

NAME_FD    FPGA dedicated function

NAME_FC    FPGA clock

NAME_U     ARM uP i/o

and so on. Sometimes we specify a bank, too. That lets The Brat pick
the pins for best routing. We rip the final netlist and feed that into
the Quartus thing, which tells us if her pin assignments are OK. In
some cases, nothing but the Altera software can decide for sure if
it's OK.

John


Re: Grundig Satellit 300 whinge
On Tue, 06 Dec 2011 20:08:08 -0800, John Larkin

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I generally use a convention sorta like:

SECTION_NAME_TYPE
  where: SECTION = controlling subsection
         NAME    = signal function
         TYPE    = I2C (SDA, SCL), SPI (SCLK, MOSI, etc.), TxD, Clock, etc

/ (prefix) = negative active.  Gets converted to "_n" suffix in the VHDL
wrapper (negative active signals are fairly rare in the logic).

+ (suffix)  = positive differential
- (suffix)  = negative differential
+V.V       = positive voltages
-V.V       = negative voltages

I don't much care if it's an FPGA or UC I/O.  I care about its function and
which section of the logic owns it.

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Do you make a good cut at the FPGA design before layout or just define the
pins and their functions?

Re: Grundig Satellit 300 whinge
On Wed, 07 Dec 2011 21:04:01 -0500, " snipped-for-privacy@att.bizzzzzzzzzzzz"

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We usually finish the board layout before we finish the FPGA design;
often we don't start the FPGA until after the board is gerbered. I do
a pin count and a sketch-level suggestion of parts
placement/routing/bank usage, and Liz makes it actually happen. A lot
of negotiation follows. I have a lot of sympathy for people who have
to use outside layout services, or throw it over the wall to another
department. I can see how they could wind up with two or three board
spins before it works.

The rules for pin usage on the Altera chips aren't all in writing, so
that's why we load the pinout into the Quartus software before we
gerber the board. We had one case recently where a cmos logic level
ball was next to an LVDS pair, and Quartus told us there would be too
much crosstalk. Fixing the layout would be almost impossible, so we
declared the signal rate on the cmos pin to be 0 Hz. That's the cheat
for that particular problem. We've also discovered some power supply
issues on certain banks for certain kinds of signals, again from the
software and not from the manuals.

John



Re: Grundig Satellit 300 whinge
On Wed, 07 Dec 2011 18:20:24 -0800, John Larkin

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the
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I've done it both ways.  It helps to have your own layout people but without
that luxury it just means working out of a hotel room while you sit over the
layouter's shoulder.  ;-)  Without direct interaction between the designer and
layout person, agreed, anything more than a trivial design is hopeless.  I've
seen the results.  :-(

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Got that part.  Some don't cut the Gerber until the FPGA is first simulated
and fit.  I've never done it that way, though.

Re: Grundig Satellit 300 whinge
On Wed, 07 Dec 2011 22:39:10 -0500, " snipped-for-privacy@att.bizzzzzzzzzzzz"

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I
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it
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the
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had
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We use the Optimum Procrastination Management methodology.

John


Re: Grundig Satellit 300 whinge

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Is that similar to "the earliest date you can't prove it won't be
finished by" estimation method?

Sylvia

Re: Grundig Satellit 300 whinge
On Thu, 08 Dec 2011 06:46:47 -0800, John Larkin

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until I
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it
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the
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(not
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thing
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broken
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had
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"No work is done before its time."

Re: Grundig Satellit 300 whinge

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Never do today what you can put off until tomorrow, because in the
meantime it may become unnecessary.

Sylvia.


Re: Grundig Satellit 300 whinge

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If it's worth doing, it's worth doing well.

The converse is also true.

--

John Devereux

Re: Grundig Satellit 300 whinge

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I once asked my boss why we were putting up with the time wasters higher
management was telling us to do, rather than getting the real work done.  His
answer was that it was better to be fired in six months for not getting the
job done than today for not doing what the big boss wanted.  In six months
there is a good chance someone else will be in even more (schedule) trouble.

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